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ADE7753
overflows. Therefore, the integration time under these conditions
with VADIV = 0 is calculated as follows:
LINE APPARENT ENERGY ACCUMULATION
The ADE7753 is designed with a special apparent energy
Time =
0 xFFFF, FFFF, FFFF
0 xD 055
× 1.2 μs = 888 s = 12.52 min(32)
accumulation mode, which simplifies the calibration process.
By using the on-chip zero-crossing detection, the ADE7753
When VADIV is set to a value different from 0, the integration
time varies, as shown in Equation 33.
Time = Time WDIV = 0 × VADIV (33)
accumulates the apparent power signal in the LVAENERGY
register for an integral number of half cycles, as shown in
Figure 77. The line apparent energy accumulation mode is
always active.
The number of half line cycles is specified in the LINECYC
register, which is an unsigned 16-bit register. The ADE7753 can
accumulate apparent power for up to 65535 combined half
cycles. Because the apparent power is integrated on the same
integral number of line cycles as the line active energy register,
these two values can be compared easily. The active energy and
the apparent energy are calculated more accurately because of
this precise timing control and provide all the information
needed for reactive power and power factor calculation. At the
end of an energy calibration cycle, the CYCEND flag in the
interrupt status register is set. If the CYCEND mask bit in the
interrupt mask register is enabled, the IRQ output also goes
active low. Thus the IRQ line can also be used to signal the end
of a calibration.
The line apparent energy accumulation uses the same signal
path as the apparent energy accumulation. The LSB size of these
two registers is equivalent.
APPARENT
POWER
%
+
+
48
0
LVAENERGY REGISTER IS
VADIV[7:0]
UPDATED EVERY LINECYC
ZERO CROSSINGS WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
LPF1
23
0
FROM
CHANNEL 2
ADC
ZERO-CROSSING
DETECTION
CALIBRATION
CONTROL
LINECYC [15:0]
LVAENERGY [23:0]
02875-0-076
Figure 77. ADE7753 Apparent Energy Calibration
Rev. C | Page 37 of 60
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